SSTL IO Standard Based Energy Efficient Digital Clock Design on 28nm FPGA
نویسندگان
چکیده
منابع مشابه
HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA
In this paper we have designed an energy efficient multiplier using Nikhilam Navatashcaramam Dashatah Vedic technique. Vedic mathematics consists of 16 sutras and these sutras were used by our ancient scholars for doing there calculation faster, when there were no computers and calculators. Nikhilam Navatasaman is a Sanskrit word which menas “all from 9 and the last from 10”. In today’s work th...
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ژورنال
عنوان ژورنال: International Journal of Control and Automation
سال: 2015
ISSN: 2005-4297,2005-4297
DOI: 10.14257/ijca.2015.8.6.05